The present technique relates to the efficient utilisation of an address translation cache.
It is known to provide data processing systems which incorporate an address translation cache, such as a translation lookaside buffer (TLB), to store address translation data relating to the translation of virtual addresses to physical addresses. The address translation data can also provide attribute data regarding the memory accesses being made, such as permission data and memory attributes. Whilst the provision of an address translation cache is useful in improving performance by reducing the number of slow page table walks required, the address translation cache itself consumes circuit resources.
It is known to create coalesced TLB entries in situations where multiple adjacent descriptors meet page alignment criteria. However, whilst creating coalesced entries can allow more efficient use of the address translation cache resources to be made, it is desirable to efficiently manage the handling of such coalesced entries so as to seek to reduce any performance impact that might otherwise result from the assigning of coalesced address translation data into the address translation cache.